December 7, 2016
FTV1643 A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High- Density Interconnects- IEEE VLSI Project 2016 - 2017

FTV1643 A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High- Density Interconnects- IEEE VLSI Project 2016 – 2017

FTV1643 A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High- Density Interconnects-  IEEE VLSI Project 2016 – 2017 […]
December 7, 2016
FTV1642 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application- IEEE VLSI Project 2016 - 2017

FTV1642 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application- IEEE VLSI Project 2016 – 2017

FTV1642 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application-  IEEE VLSI Project 2016 – 2017 ABSTRACT: A new design procedure has been proposed for […]
December 7, 2016
FTEEE1627-A-New-Compact-and-High-Efficiency-Resonant-Converter-IEEE-EEE-Project-2016-2017

FTEEE-1627 A New Compact and High Efficiency Resonant Converter – IEEE EEE Project 2016 – 2017

FTEEE-1627 A New Compact and High Efficiency Resonant Converter – IEEE EEE Project 2016 – 2017 ABSTRACT: A new resonant converter which features compact size, high efficiency, […]
December 7, 2016
FTV1641 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell- IEEE VLSI Project 2016 - 2017

FTV1641 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell- IEEE VLSI Project 2016 – 2017

FTV1641 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell-  IEEE VLSI Project 2016 – 2017 ABSTRACT: A novel 8-transistor (8T) static random access memory […]
December 7, 2016
FTV1633 Design and FPGA Implementation of a Reconfigurable 1024- Channel Channelization Architecture for SDR Application- IEEE VLSI Project 2016 - 2017

FTV1633 Design and FPGA Implementation of a Reconfigurable 1024- Channel Channelization Architecture for SDR Application- IEEE VLSI Project 2016 – 2017

FTV1633 Design and FPGA Implementation of a Reconfigurable 1024- Channel Channelization Architecture for SDR Application-  IEEE VLSI Project 2016 – 2017 ABSTRACT: We present a novel […]