Compaction of Schedules and a Two-Stage Approach for
Duplication-Based DAG Scheduling : IEEE 2009
Many DAG scheduling algorithms generate schedules that require prohibitively large number of processors. To address this problem, we propose a generic algorithm, sc, to minimize the processor requirement of any given valid schedule. sc preserves the schedule length of the original schedule and reduces processor count by merging processor schedules and removing redundant duplicate tasks. To the best of our knowledge, this is the first algorithm to address this highly unexplored aspect of DAG scheduling. On average, screduced the processor requirement 91, 82, and 72 percent for schedules generated by plw, tcsd, and cpfd algorithms, respectively. sc algorithm has a low complexity (O(|N|3)) compared to most duplication-based algorithms. Moreover, it decouples processor economization from schedule length minimization problem. To take advantage of these features of sc, we also propose a scheduling algorithm sds, having the same time complexity as sc. Our experiments demonstrate that schedules generated by sds are only 3 percent longer than cpfd (O(|N|4)), one of the best algorithms in that respect. sds and sc together form a two-stage scheduling algorithm that produces schedules with high quality and low processor requirement, and has lower complexity than the comparable algorithms that produce similar high-quality results.
nhanced performance and reduced cost of commodity hardware boosted employment of distributed memory multiprocessor systems (DMMS) in supercomputing fields, such as climate research, physical simulations, image processing, and database systems. In many applications, an efficient parallel version of the application program is not available. Therefore, parallelism is achieved by partitioning the program into smaller chunks, called tasks, and scheduling these tasks on target DMMS to minimize the overall execution time, or schedule length.
The goal of partitioning is to represent the program in the form of a directed acyclic graph (DAG) consisting of tasks with appropriate grain size , . Task computation and intertask communication times in the DAG are determined according to the target DMMS architecture via estimation and benchmarking techniques , , . Dependencies among tasks incur inevitable communication overhead when tasks are assigned to different processors of the
- Bozdag is with the Department of Electrical and Computer Engineering, The Ohio State University, 333 W. 10th Avenue, 3190 Graves Hall, Columbus, OH 43210. E-mail: firstname.lastname@example.org.
- Ozguner is with the Department of Electrical and Computer Engineering, The Ohio State University, 205 Dreese Laboratory, 2015 Neil Avenue, Columbus, OH 43210. E-mail: email@example.com.
- V. Catalyurek is with the Department of Biomedical Informatics, The Ohio State University, 333 W. 10th Avenue, 3172B Graves Hall, Columbus, OH 43210 and the Department of Electrical and Computer Engineering, The Ohio State University, 316 Dreese Laboratory, 2015, Neil Avenue, Columbus, OH 43210. E-mail: firstname.lastname@example.org.
We developed a novel algorithm to minimize the processor requirement of schedules generated by any scheduling algorithm. When applied on a valid schedule, the proposed SC algorithm compacts the schedule on fewer number of processors without increasing the schedule length. Experiments on DAGs representing three applications as well as random DAGs verified that SC algorithm dramatically reduces the processor requirement of the schedules generated by CPFD, PLW, and TCSD algorithms. For our test set, the reduction was 91 percent for PLW, 82 percent for TCSD, and 72 percent for CPFD algorithms on average. SC algorithm has a time complexity of O(|N|3), which is smaller than most duplication-based scheduling algorithms.
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